As used herein, the term "high voltage" refers to voltages of nominally more than 5 volts; the term "low voltage" refers to voltages of 5 volts or less, being typically 3.3 volts or less. The term "high voltage transistor" refers to a transistor designed to operate with a minimum of degradation at a high voltage (e.g., a thick-oxide transistor); and the term "low voltage transistor" refers to a transistor designed to operate only at a low voltage (e.g., a low-voltage CMOS transistor).
The use of embedded flash EEPROM (Electronically Erasable Programmable Read Only Memory) in cellular phones, answering machines, cordless phones and other devices containing silicon integrated circuits is increasing. Current generation flash EEPROMs require the use of circuitry and thick-oxide transistors capable of handling high voltages (e.g., typically 7 volts) in the critical read column precharge path for erasing and programming (writing) the flash memory cells because the columns must be raised to high voltages during erase and programming operations (hereinafter referred to collectively as "high voltage memory operations"). However, the use of high voltage transistors in EEPROMs has negative effects on performance. For instance, high voltage transistors operated at high voltages are subject to parameter degradation and are inherently less reliable than low voltage core CMOS transistors operated at lower voltages (e.g., less than 5 volts, typically about 3 volts). Read precharge and cycle times also are increased when high voltage transistors are used in the critical read column precharge path because of their significantly lower gain (typically less than one-half the gain of low voltage core CMOS transistors).
FIG. 1 illustrates a typical EEPROM circuit 10 of the prior art. FIG. 1 shows a flash EEPROM memory array 20 having N columns (C.sub.1, C.sub.2, . . . C.sub.N) and M rows (R.sub.1, R.sub.2, . . . R.sub.M), an associated on-pitch sense amplifier block 30, column select transistor block 40, high voltage column precharge transistor block 50, and write/erase data transfer gate block 60.
Each memory cell in memory array 20 comprises a floating gate transistor in which the drain terminal is coupled to the associated column, the gate terminal is coupled to the associated row, and the source terminal is coupled to a source. In essence, a floating gate transistor comprises a first gate, the floating gate, positioned above the current channel of the transistor and separated therefrom by a layer of insulation (e.g., oxide) and a second gate, the fixed gate, positioned above the first gate and separated therefrom by another layer of insulation. The fixed gate is directly coupled to the gate terminal of the transistor. Both stacked gate and split gate designs are known in the art.
The column precharge transistor block 50 comprises a thick oxide, high voltage transistors 51(1), 51(2), . . . 51(N) coupled to each column, respectively.
As is known in the art, in order to read a flash memory cell, the column associated with that cell must be precharged to a specific voltage, e.g., 1 volt. If that cell has been written to, that is, if it stores a logic 1, then the transistor comprising that cell will remain off when the corresponding row is asserted and will not discharge the voltage that was placed on the column through the precharge transistor. If, on the other hand, the memory cell is erased, that is, if it stores a digital 0, then that cell will be turned on when the corresponding row is asserted, thus driving the column to ground through the source-drain path of the memory cell transistor.
The sense amplifiers 30(1),30(2), . . . 30(m) amplify the column voltage as set by the cell on that column that is being read to produce an output.
As is known in the art, when erasing a flash EEPROM memory array, the columns (drain terminals of the memory cells) are raised to a high voltage, typically 7 volts, while the rows (gate terminals), R.sub.1, R.sub.2, . . . ,R.sub.M, are kept at ground (0 volts) or reduced to a negative potential below ground. The source is commonly open circuited for erasing. The high gate to drain voltage differential causes electron tunneling from the drain of the transistor to the floating gate, raising the nominal potential of the floating gate. Enough electron tunneling is allowed to occur to raise the nominal potential of the floating gate to a point at which it will rise above the transistor's threshold current when the corresponding row is asserted (i.e., when the fixed gate is raised to a logic high level, such as 3.3 volts). This will cause the transistor to conduct when the corresponding row is asserted (for reading that cell), thus driving the corresponding column to ground.
When writing a flash EEPROM memory array 20, columns (gates) associated with cells to be written (i.e., that are to store a digital 1) are raised to a high potential, typically 7 volts, as are the rows (drains) associated with the cells to be written. The source terminals are grounded. Other columns associated with cells along the same row that are not being written remain at ground. This condition causes hot electron injection from the current channel to the floating gate, thus lowering the nominal potential of the floating gate. Enough electron injection is allowed to occur to lower the nominal potential of the floating gate to a point at which, even when the gate terminal is raised to 3 volts, i.e., when the corresponding row is asserted, the floating gate will still be below the threshold voltage such that the transistor will not conduct. Accordingly, the column will not be discharged and the cell will be read as logic 1.
It can, therefore, be seen that, when erasing or writing a cell, it is necessary to raise the associated column to a high voltage level. Accordingly, the column precharge transistors, having their drain terminal coupled to the columns, must be high-voltage, thick oxide, transistors in order to handle the high voltage. During erase and write operations, the gates of precharge transistors 51(1), 51(2), . . . 51(N) are at ground (0 volts) along PRECHARGE input 52. This results in a high gate-to-drain potential (e.g., 7 volts) for each transistor, which is easily withstood by the high voltage transistors, but which would destroy low voltage core CMOS transistors.
With reference to the first column C.sub.1 in FIG. 1, the method and circuitry of the prior art will be described. For erase and write operations, prior to applying high voltage to inputs D.sub.1 and RC.sub.1, the precharge input 52 must be set to ground to prevent conduction through the precharge transistor 51(1) within precharge block 50. Also, in preparation for applying high voltage to the first column C.sub.1 for writing/erasing, a high voltage, typically 7 volts, is applied to the data input D.sub.1 and the read control input RC.sub.1 of the write/erase data transfer gate block 60. This sets up the data, but blocks conduction through devices M7 and M8.
If the entire memory is being erased, all data input terminals D.sub.1, . . . D.sub.n receive the high voltage. For programming, however, only the column containing the cell or cells being programmed are charged.
Then, the write or erase is initiated by lowering the read control input RC.sub.1, thus allowing the high voltage applied to data input D.sub.1 to be transferred onto column C1. Specifically, lowering the read control input RC.sub.1, turns on devices M7 and M8, passing the high voltage from data input D.sub.1 onto the column.
If the operation is a write, then, for those columns associated with cells not to be written, but along the same row as other cells being written, their voltage is kept at ground by keeping their data inputs (i.e., D.sub.1, D.sub.2, . . . D.sub.N) at ground.
The column select transistor block 40 and sense amplifier block 30 are used for reading the flash memory. Particularly, the column enable signal coupled to the gates of the transistors 41(1), 41(2), . . . 41(N) is asserted, thus turning those transistors on so that the column voltage can be sensed by the sense amplifier block 30. The sense amplifiers 30(1), 30(2), . . . 30(N) amplify the column voltage to the logic high level for the circuit (e.g., 3.3 volts and hereinafter termed "VDD" ), if the column is at 1 volt. If the column is grounded through a memory cell transistor, then the output of the sense amplifier also is at ground.
Care must be taken not to over-voltage stress the transistors 41(1), 41(2), . . . 41(N) during writing or erasing. If column select transistors 41(1), 41(2) . . . 41(N) in column select block 40 are low voltage transistors, their gates (COLEN input 42) must be set to VDD level (e.g. 3.3 volts) prior to raising the column voltage above VDD. Otherwise the gate-to-drain voltage will go to a high voltage and possibly damage the transistor's gate oxide. With their gates at VDD and the columns raised high, the inputs to the sense amplifiers(s) (N.sub.1, N.sub.2 . . . , N.sub.n) will be VDD-Vt. This will not over-stress any transistors in the sense amplifier. Alternatively, the column select transistors 41(1), 41(2) . . . 41(N) in the column select transistor block 40 could be high voltage transistors. In this case COLEN input 42 can be set at ground, blocking conduction through these devices.
The precharge transistors, 51(1), 51(2), . . . 51(N), are high voltage, thick oxide, transistors in order to handle the high level write and erase voltages. High voltage transistors have low gain because of the thick oxide. Use of these low gain transistors in the precharge block 50 limits circuit performance by increasing precharge and cycle times. The characteristics of high voltage transistors also degrade over time when operated at high voltages. This degradation may, over time, further lengthen precharge time.
Since the write/erase data inputs D.sub.1, D.sub.2, . . . D.sub.N and the read control signal input RC.sub.1 of write/erase data transfer gate block 60 must be at high voltage levels when asserted to carry out the write and erase functions, not only are the transistors in the write/erase data transfer gate block 60 (e.g., transistors M.sub.7 and M.sub.8) high voltage, thick oxide, transistors, but the off-pitch circuitry (not shown) needed to generate the high voltage signals on lines D.sub.1, D.sub.2, . . . D.sub.N must also include high voltage transistors.
Because high voltage transistors are generally less reliable than low voltage transistors, the use of so many high voltage transistors also may lead to less reliable EEPROM operation.
In addition, there is a significant amount of capacitance associated with each column. Particularly, each memory cell has an associated capacitance. The greater the capacitance on a column, the slower the column will precharge and discharge for read operations.
In order to reduce the effective capacitance, it is known in the art to divide each column into smaller column segments that are individually precharged and discharged for reading. FIG. 2 is a circuit diagram of a flash EEPROM of the prior art with segmented columns. FIG. 3 is a more detailed diagram of an individual column segment of the circuit shown in FIG. 2. Sense amplifier block 130, column select block 140, column precharge transistor block 160 and write erase block 160 are essentially identical to blocks 30, 40, 50 and 60 respectively, in the circuit of FIG. 1.
For instance, if a global column, e.g., 120(1), comprises 256 cells, it may be divided into four column segments, i.e., COLSEG.sub.-- 1.sub.-- 1, COLSEG.sub.-- 2.sub.-- 1, . . . COLSEG.sub.-- 4.sub.-- 1, each comprising 64 cells. In this manner, the effective capacitance during a read operation can be cut by a factor of 4. As shown in FIG. 3, each column segment comprises memory cells 102(1), 102(2), . . . 102(N). As before, the control gates of the cells are individually coupled to the rows, the source terminals of the cells are all coupled together to a voltage source and the drains of the cells are all coupled to the column segment. The column segment is coupled to the global column through a column segment select switch 104. As can be seen in FIG. 2, each column segment is coupled to the global column through a switch such as switch 104. A segment select signal line 110 and its inverse are coupled to the corresponding transistors, respectively, of the column segment select switches 104.
Switch 104 comprises two complementary, high voltage, thick oxide, transistors 106 and 108. The transistors are high voltage transistors because they need to pass 7 volts with as much as a 1/4 milliamp of current to the column during write operations. Two complementary transistors are desirable because, as is known in the art, n-channel transistors pull down well, but do not pull up well, whereas p-channel transistors pull up well, but do not pull down well. The column segment select switch 104 has an n-channel device to most effectively pull the sense amplifier input towards ground for reading (when the accessed cell stores a 0) and has a p-channel device for the high voltage memory operations (erase and program) to most effectively pull the column up to the high voltage level needed on the drain terminal of the cell for programming (i.e., writing) or erasing cells.
The segmented column array architecture is well suited for fast, low power, read operations because only one column segment per column is precharged and discharged during a read cycle. Because the capacitance of a column segment has only a fraction of the capacitance of the global column, the precharge/discharge time and power also are reduced to only a fraction of what would have been needed to precharge/discharge the global column.
However, the improvement in performance is diminished somewhat because high voltage transistors such as transistors 106 and 108 of switch 104 have relatively high parasitic capacitance as well as low gain. Accordingly, switch 104 adds undesirable parasitic capacitance to the column segment and reduce read operation speed because of its low gain in the sensing and column precharge paths.
Further, the high voltage, low gain, transistors in the column precharge block 50 and write/erase data transfer gate block 60 remain in the circuit, with their inherent drawbacks.